Compile prepared statements
Compilation preprocessing is an integral part of the verilog hdl compilation system. The compiled preprocessing statement starts with (`) in the wavy line below esc
When compiling, the compiling system first preprocesses the compiled preprocessing statement, and then compiles the processing result together with the source program
define statement
Macro definition statement - use a specified identifier (ie macro name) to represent a string (ie macro content)
Format
`define Identifier (i.e. macro name) string (i.e. macro content)
ps compiles the prepared statement, there is no semicolon after writing
example:
`define IN ina+inb+inc+ind
Macro expansion --- the process of replacing macro names with strings during compilation preprocessing
The role of macro definition:
replace a long string or complex expression with a simple name;
Replace meaningless numbers and symbols with a meaningful name;
Macro names should be expressed in capital letters as much as possible to distinguish them from variable names
`define can be written in front of the module or inside the module. The valid range of the macro name is from the definition command to the end of the source file
module test; reg a,b,c,d,e,out; define expression a+b+c+d //Must not add;, otherwise, when quoting later, out = a+b+c+d;+e will report an error assign out = `expression + e; endmodule
When defining a macro, you can refer to the defined macro name to achieve layer-by-layer replacement;
module test; reg a,b,c; wire out; `define aa a+b //no semicolons `define cc c+'aa //Reference macro name `aa to define macro `cc assign out = `cc; endmodule
The difference between macro definition and parameter
scope | |
`define | the whole project |
parameter | Valid in this module |
localparam | It is valid in this module and cannot be used for passing parameters |
`include statement
File include statement, a source file can include the full name of another source file
Format: `include <file name> is the relative path relative to the sim or the real path of the file

ps: It is equivalent to assigning all the contents of file2.v to the place where the `include"file2.v" command appears
An include statement can only specify one included file: to include n files, n include statements are required
`include "aa.v""bb.v"//It is wrong to write this way, it can be written as the following form `include "aa.v" `include "bb.v"
The `include statement can appear anywhere in the source program, the included file is weaker than the included file is not in the same subdirectory, and the path must be specified
`include "parts/count.v"
effect
It can reduce the repetitive labor of program developers
Design 16-bit adder with include statement
//1'bit adder moudule adder (cout,sum,a,b.cin); parameter size = 1; input [size-1:0]a,b;//bit width is 1 input cin; output sum; output cout; assign {cout,sum} = a + b + cin;cout Store the carry value, sum save low sum,{cout,sum}is bit splicing endmodule `include "adder.v" module adder_16b (cout,sum,a,b,cin); output cout; parameter my_size = 16; output [my_size-1:0] sum; input [my_size-1:0] a,b; input cin; adder #(my_size) my_adder(cout,sum,a,b,cin);//Module instantiation of adder, the parameter in my_adder becomes my_size=16 endmodule
adder #(my_size) my_adder(cout,sum,a,b,cin); parameter can be passed by name or position
Joining is that multiple parameters can be passed by position or name
adder #(my_size1,my_size2) my_adder(cout,sum,a,b,cin);//This method is position parameter passing
adder #(.size1(my_size1),.size2(my_size2)) my_adder(cout,sum,a,b,cin);//This method is the parameter name
monitor usage
`timescale statement
Used to define the time unit and time precision of the module following this command
Format: `timescale<time unit>/<time precision>
Time unit: the base unit used to define the simulation time and delay time in the module;
Time accuracy: used to declare the accuracy of the simulation time and delay time of the module;
Modules with different time units can be included in the same program design. (At this time, the minimum time precision value is used to determine the time unit of the simulation)
The time precision must be at least as precise as the time unit, and the time precision value cannot be greater than the time unit value!
In the timescale statement, the numbers used to specify the time unit and time precision parameter values must be integers
Its valid figures are 1, 10, 100;
The unit is second (s), millisecond (ms), microsecond (us), nanosecond (ns), picosecond (ps), millipicosecond (fs)
eg:
`timescale 10ns/1ns//The time unit is 10ns, and the time precision is 1ns ..... reg sel; initial begin #10 sel = 0;//delay 10 time units #10 sel = 1;//delay 10 time units end