ic Verification notes - 20 day challenge Day5 two

1.sv interface

interface can be used in hardware domain and software domain

The data-driven relationship between dut and tb can be realized by interface

interface arb_if(input bit clk);

        logic [1:0] grant, request;

        logic rst;


module arb(arb_if arbif);


        always @(posedge arbif.clk or posedge arbif.rst) begin


                        arbif.grant <= 2'b00;


                        arbif.grant  <= next_grant;




module test (arb_if arbif);
    initial begin 
        //reset code left out
        @(posedge arbif.clk) arbif.request <= 2'b01;
        $display("@%0t: Drove req=01", $time);
        repeat(2) @(posedge arbif.clk);
        if(arbif.grant != 2'b01) $display("@%0t: a1:grant != 2'b01", $time);
endmodule: test

interface can define parameters, input and output ports, functions and tasks, and process code blocks

2. Sampling and data driven

2.1 delay of sampling and driving

In order to avoid the problem of signal competition in RTL simulation behavior, the problem of synchronization is solved by non blocking assignment or signal delay

a = a+1;

b = a;

The rising edge of the clock and the signal assignment of the data; When the clock drives the combinational circuit, an infinitesimal delay (delta_cycle) (time unit: s,ms, us,ns,ps,fs) will be added by default

expanded time deltas mode

data will be in t+1*delta_cycle changes

2.2 clock block in interface

clocking bus @(posedge clock1);//Rising edge to drive and sample

        default input  #10ns output #2ns / / input sampling is performed 10ns before the rising edge, and output driving is performed 2ns after the event

        input data, ready, enable;

        output negedge ack;//Falling edge drive

        input #1step addr;// 1step before rising edge (time slice)


3. Testing and commissioning

3.1 testing

The verilog function is required to actively end the simulation $finish() at the end of the simulation

run 0 

assign will be executed at time 0, but it will be executed only when the signal changes such as always

Implicit end of program

Put the design into module and the test sample into program; The internal variables of the program are assigned with blocking assignment, and the external hardware signals are driven with non blocking assignment

module instantiation and always blocks cannot be used in the program software domain

3.2 commissioning

library is the product of compilation. After compilation, it is put into library(work) by default. If you want to use the package of other libraries, you need to configure the config file;

The sim window simulation window shows the structural hierarchy of TB and DUT (design under test)

The process window represents the status of initial, assign and always of the simulation at a certain time point. If the status is active, it indicates that the improvement process block is running. If it is ready, it indicates that the process block is inactive;

View signals and waveforms


Click a certain level in the sim window, and then add an appropriate signal to the wave in the objects window to force the value of the signal to be modified. In the objects window, right-click the signal whose value you want to change, and modify - > force

Use the toolbar to quickly jump to the changing edge of the signal

Using log -r / * in script can save waveforms

$display() shows the time when the message occurs by passing $time, $display() shows different data formats,% X (hexadecimal),% d (decimal),% b (binary),% s (string),% t (time)

$display() message level, $warning() (warning level), $error() (error level), $fatal() (severity level)

Formatting of string $sformatf()

string s = $sformatf("Hello, %s!", name_s)

Set a breakpoint to view the value change of local variables, view the dynamic variable locals window, and view - > locals in the menu bar

wave displays the value generated after the delta cycle is run

Press expanded time at active cusor

Software signal value, dynamic variable locals, hardware signal, static variable objects

Similarly, the value of dynamic variable running twice is 1, while the value of static variable is 2

Adjust the hexadecimal display of the signal, right-click the signal and modify the radix

Check the signal time interval in the wave window, and add cursor under the third bottom

Posted by egpis on Mon, 18 Apr 2022 22:49:15 +0930