FPGA learning notes
If you need to finish the design, you can take notes by yourself Xiaomeige loves drifting Wildfire 0 FPGA overview 0.1 basic Verilog syntax 1 development process 1.1 case: control LED lamp 1.2 case: 3-8 decoder (more detailed) 2. Hierarchical design 2.1 case: full adder Performance comparison bUTF-8...
Posted by gbuck on Tue, 18 May 2021 03:49:02 +0930
Simulation test platform file (TestBench)
A test platform file is a VHDL model, which can be used to verify the correctness of the designed hardware model. The test platform file provides excitation signals for the tested components, and the simulation results can be displayed or stored in the file in the form of waveform. The excitatUTF-8...
Posted by SulleyMonstersInc on Tue, 13 Jul 2021 07:15:37 +0930
Detailed explanation of HEX(Xilinx MCS) file format
hex file refers to a file with hex as suffix and Intel hex coding rules. It can be opened directly with text editing tools. It is usually used to program microcontroller or ROM. in essence, it is to program memory, which contains the data corresponding to each address. Xilinx mcs file used forUTF-8...
Posted by ruthsimon on Sun, 25 Jul 2021 08:35:07 +0930
ALTDDIO_IN,ALTDDIO_ Simulation of out IP core (double data rate I/O, DDIO)
1. Foreword ALTDDIO_IN,ALTDDIO_OUT is a double data rate (DDR) IP core provided by Altera. The DDR IP core can be used to implement DDR registers in logical resources. ALTDDIO_ The in can receive data on the rising and falling edges of the reference clock through the DDR interface; ALTDDIO_OUT UTF-8...
Posted by Kazhultee on Thu, 23 Dec 2021 22:08:51 +1030
[detailed explanation + example] verilog blocking and non blocking analysis -- hierarchical event queue
1. Introduction to hierarchical event queue A detailed understanding of Verilog's hierarchical event queue helps us understand Verilog's blocking and non blocking assignment functions. The so-called hierarchical event queue refers to different Verilog event queues used to schedule simulation evUTF-8...
Posted by mepaco on Mon, 27 Dec 2021 22:07:20 +1030
[introduction 2] code and principle explanation of buzzer ringing based on FPGA and Verilog
Last blog post: [introduction 1] explanation of key lighting code and principle based on FPGA and Verilog Function Description: using the keys learned in the previous article, this article further uses the keys. After clicking the keys, the buzzer can play different songs 1, Knowledge understaUTF-8...
Posted by philspliff on Wed, 19 Jan 2022 10:11:43 +1030
Design of ultrasonic ranging based on nexys 4 development board
Basic experimental requirements 1.Control ultrasonic transmitting and receiving sensors 2.Real time display of obstacle distance through nixie tube 3.Distance below or above threshold LED Blue and red are displayed, and green is displayed within the normal distance range 4.The threshold distanUTF-8...
Posted by arsitek on Sat, 22 Jan 2022 09:42:55 +1030
Three communication protocols UART
catalogue 1, Introduction to UART communication protocol 2, UART communication sequence 3, UART, RS232, TTL relationship description 1. Introduction 2. Level conversion 4, Examples 1. Program code 2. Simulation verification Summary 1, Introduction to UART communication protocol UART (UniversalUTF-8...
Posted by CreativeWebDsign on Tue, 25 Jan 2022 17:10:11 +1030
Basic data types in verilog
The two most commonly used data types of Verilog are wire and reg ister. The other types can be understood as the extension or assistance of these two data types. 1, wire Wire type refers to the physical connection between hardware units, which is continuously driven by the connected device outUTF-8...
Posted by htcilt on Mon, 31 Jan 2022 07:38:22 +1030
[ROM IP] Vivado ROM IP core call experiment
ROM IP core call experiment 1. Introduction to ROM IP core ROM is the abbreviation of read only memory. It is a solid-state semiconductor memory that can only read the data stored in advance. Its characteristic is that once the data is stored, it can no longer be changed or deleted, and the datUTF-8...
Posted by Stray_Bullet on Mon, 31 Jan 2022 16:34:43 +1030