Experimental report on 2020 course design of computer composition principles of Guangzhou University

1, The nature, purpose and task of this course design

Course design of computer composition and system structure is one of the concentrated practical links of various majors in the computer college. It is a comprehensive exercise after learning the course of computer composition and system structure. Its purpose is to design and implement a model computer by comprehensively using the learned computer principle knowledge, so as to consolidate the learned knowledge and improve the ability to analyze and solve problems.

2, Basic theory of this course design

1. Master arithmetic, logic and shift operation experiments, and be familiar with the application of ALU operation control bit.

2. Master the memory organization, reading and writing mode and the data path composed of the general route, and master the working principle of address bus and data bus.

3. Master the instruction structure and instruction taking and execution process.

4. Master the micro program control principle of CPU.

3, Title

1. Comprehensively use the learned computer principle knowledge to design and implement the model computer with the following instruction set structure:

number

Mnemonic

machine instruction code

explain

0

SUB  Rd,Rs

1000 RdRs 

Rd-Rs→Rd

1

ADD  Rd,Rs

1001 RdRs 

Rd+Rs→Rd

2

AND  Rd,Rs

1010 RdRs 

RD & Rs → Rd (RD and Rs phase with each other)

3

DEC Rd

1011 Rd00

Reduce the Rd value by 1

4

CLR Rd

1100 Rd00

Clear Rd to zero

5

RL  Rd

1101 Rd00  

Rd cycle shifts left one bit

6

RRC  Rd

1110 Rd00

Rd with carry shifted right by one bit

7

MOV Rd,Rs 

1111 RdRs

Rs→Rd

8

LDI  Rd,*

0000 Rd00   XXXXXXXX

Send the immediate number (second byte) in the instruction to Rd

9

OUT  IOH,Rs

0001 00Rs

Rs → I / O (data switch) high byte

10

LDA  Rd,M

0010 Rd00   XXXXXXXX   XXXXXXXX

[M] →Rd

11

STA  M,Rs

0011 00Rs   XXXXXXXX   XXXXXXXX

Rs→[M]

12

JMP M

0100 0000  XXXXXXXX   XXXXXXXX

[M] → PC, i.e. jump to the unit indicated by M

13

JZ M

0101 0000  XXXXXXXX   XXXXXXXX

When Z=1, jump to the cell indicated by M

14

JC M

0110 0000  XXXXXXXX   XXXXXXXX

When CY=1, jump to the unit indicated by M

15

HALT

0111 0000

Shut down

2. Design tips:

1) In the above table, the upper 4 bits of the machine instruction code are the instruction operation code, M is the 16 bit memory address, Rs is the source register and Rd is the destination register, accounting for 2 bits. It is specified that:

Rs or Rd

Selected register

00

01

10

11

R0

R1

R2

R3

2) In the microprogram, the micro address 001 is the index.

3) How to determine the microprogram entry address in each instruction finger line stage:

Micro address tag number

10   9

8   7  6   5

4  3  2  1  0

content

1    1

IR7~IR4

0  0  0  0  0

For example, the instruction code of the 5th instruction "RL ^ Rd" is 0101 Rd00 ^ then the upper four bits IR7~IR4 of the instruction code are 0101. As can be seen from the above table, the micro address of the microprogram entry is 11 0101 00000, i.e. 6A0H.

Note: bits 10 and 9 are from bits 10 and 9 of the value set by upc in the 0001 microinstruction. For example, 11 for 600 and 10 for 400

3. Main steps:

(1) According to the method in point 3, the microprogram entry micro address of all 16 instructions is given;

(2) By analyzing the function of each instruction to clarify its microprogram flow, refer to Fig. 3-4-1, FIG. 3-2-2 and Fig. 3-3-1 of the experimental instruction;

(3) Write the micro command of each micro instruction, i.e. 24 micro control bit signals. Refer to table 3.4.1, table 3.2.1, table 3.3.1 of the experimental instruction and Chapter 2 of the "microcontroller programming manual".

(4) It is suggested to design and implement one instruction by one. After one instruction is implemented and tested with assembly statements (the instruction function and address sequence are correct), the next one can be designed.

5. Check

After the model computer design IS completed, check with the given test program_ 1. ASM (test 12 non transfer instructions) and check_ 2. Check the correctness of ASM (test 3 transfer instructions). Inspection method: use #s my own in the test program IS micro instruction program, turn off the power of the experimental box, restart and connect, and select "run" or "single step" after loading.

check_ The operation results of register r00133 and register r00133 are displayed as correct respectively.

check_ 2. The correct result of ASM operation is that register R0R1R2R3 displays 00112233 respectively. If EE is displayed, there is an error in execution.

4, Model machine instruction system (given in list form, including mnemonics, operands, instruction codes, lengths, comments, etc.)

; Complex model machine instruction system

;Mnemonic operand              Instruction code length

;-----------------------------------------------------

LDI     R0,*               00     2;

LDI     R1,*               04     2;

LDI     R2,*               08     2;

LDI     R3,*               0C     2;  Send the immediate number (second byte) in the instruction to



OUT     IOH,R0             10     1;

OUT     IOH,R1             11     1;

OUT     IOH,R2             12     1;

OUT     IOH,R3             13     1;  Rs→I/O(Data switch)High byte



STA     *,R0               30     3;

STA     *,R1               31     3;

STA     *,R2               32     3;

STA     *,R3               33     3;   Rs→[M]



JMP     *                  40     3; [M]→PC,Jump to M Indicated unit

JZ      *                  50     3; When Z=1 When, jump to M Indicated unit

JC      *                  60     3; When CY=1 When, jump to M Indicated unit

HALT    ""                 70     1;Shut down(Bus lock)



SUB     R0,R0              80     1

SUB     R0,R1              81     1

SUB     R0,R2              82     1

SUB     R0,R3              83     1

SUB     R1,R0              84     1

SUB     R1,R1              85     1

SUB     R1,R2              86     1

SUB     R1,R3              87     1

SUB     R2,R0              88     1

SUB     R2,R1              89     1

SUB     R2,R2              8A     1

SUB     R2,R3              8B     1

SUB     R3,R0              8C     1

SUB     R3,R1              8D     1

SUB     R3,R2              8E     1

SUB     R3,R3              8F     1 ;Subtraction, Rd-Rs→Rd



ADD     R0,R0              90     1

ADD     R0,R1              91     1

ADD     R0,R2              92     1

ADD     R0,R3              93     1

ADD     R1,R0              94     1

ADD     R1,R1              95     1

ADD     R1,R2              96     1

ADD     R1,R3              97     1

ADD     R2,R0              98     1

ADD     R2,R1              99     1

ADD     R2,R2              9A     1

ADD     R2,R3              9B     1

ADD     R3,R0              9C     1

ADD     R3,R1              9D     1

ADD     R3,R2              9E     1

ADD     R3,R3              9F     1 ;Addition, Rd-Rs→Rd



AND     R0,R0              A0     1

AND     R0,R1              A1     1

AND     R0,R2              A2     1

AND     R0,R3              A3     1

AND     R1,R0              A4     1

AND     R1,R1              A5     1

AND     R1,R2              A6     1

AND     R1,R3              A7     1

AND     R2,R0              A8     1

AND     R2,R1              A9     1

AND     R2,R2              AA     1

AND     R2,R3              AB     1

AND     R3,R0              AC     1

AND     R3,R1              AD     1

AND     R3,R2              AE     1

AND     R3,R3              AF     1 ;Rd&Rs→Rd (Rd and Rs (phase and)



DEC     R0                 B0     1;

DEC     R1                 B4     1;

DEC     R2                 B8     1;

DEC     R3                 BC     1;take Rd Value minus 1



CLR     R0                 C0     1;

CLR     R1                 C4     1;

CLR     R2                 C8     1;

CLR     R3                 CC     1;take Rd Clear



LDA     R0,*               20     3;

LDA     R1,*               24     3;

LDA     R2,*               28     3;

LDA     R3,*               2C     3;[M] →Rd



RL      R0                 D0     1;

RL      R1                 D4     1;

RL      R2                 D8     1;

RL      R3                 DC     1;Rd Rotate left one bit



RRC     R0                 E0     1;

RRC     R1                 E4     1;

RRC     R2                 E8     1;

RRC     R3                 EC     1;Rd Shift right one bit with carry



MOV     R0,R0              F0     1;

MOV     R0,R1              F1     1;

MOV     R0,R2              F2     1;

MOV     R0,R3              F3     1;

MOV     R1,R0              F4     1;

MOV     R1,R1              F5     1;

MOV     R1,R2              F6     1;

MOV     R1,R3              F7     1;

MOV     R2,R0              F8     1;

MOV     R2,R1              F9     1;

MOV     R2,R2              FA     1;

MOV     R2,R3              FB     1;

MOV     R3,R0              FC     1;

MOV     R3,R1              FD     1;

MOV     R3,R2              FE     1;

MOV     R3,R3              FF     1;  Rs→Rd

6, Draw the microprogram flow chart

7, Fill in the following micro instruction table (only fill in the relevant lines with micro instructions):

Micro address 00002) 1)

M23

M22

M21

M20

M19

M18

M17

M16

code

M15

M14

M13

M12

M11

M10

M9

M8

code

M7

M6

M5

M4

M3

M2

M1

M0

code

Subsequent micro address

explain

E/M

IP

MWR

R/M

o2

o1

O0

OP

M

CN

S2

S2

S0

X2

X1

X0

XP

W

ALU

Iu

IE

IR

Icz

Ids

0000

0

0

0

0

0

0

0

0

00

0

0

0

0

0

0

0

0

00

0

0

0

0

0

0

0

0

00

0001

Empty operation

0001

0

1

0

0

0

0

0

0

40

0

0

0

0

0

0

0

0

00

0

0

0

0

0

1

1

1

07

0600

IBUS->IR

0600

0

0

0

0

0

1

0

1

05

0

0

0

0

0

1

0

0

04

0

0

0

0

0

0

0

0

00

+1

ROM->BX

0601

0

1

0

0

1

1

1

1

4F

0

0

1

1

1

0

0

1

39

1

0

0

1

0

0

1

0

92

0001

BX->RD

0620

0

0

0

0

1

0

1

0

0A

0

0

0

0

0

1

1

0

06

0

0

0

1

0

0

1

0

12

0001

RS->IOH

0640

0

0

0

0

0

1

0

1

05

0

0

0

0

0

1

0

0

04

0

0

1

0

0

0

0

0

20

+1

ROM->BL

0641

0

1

0

0

0

1

0

0

44

0

0

1

1

0

1

0

0

34

0

0

1

0

0

0

0

0

20

+1

R0M->BH

0642

0

1

0

0

0

0

1

1

43

0

0

1

1

1

0

0

1

39

1

1

0

0

0

0

0

0

C0

+1

BX->AR

0643

1

0

0

0

1

1

1

1

8F

0

0

0

0

0

1

0

0

04

0

0

0

1

0

0

1

0

12

0001

RAM->RD

0660

0

0

0

0

0

1

0

1

05

0

0

0

0

0

1

0

0

04

1

0

0

0

0

0

0

0

80

+1

ROM->BL

0661

0

1

0

0

0

1

0

0

44

0

0

0

0

0

1

0

0

04

0

0

0

0

0

0

0

0

00

+1

ROM->BH

0662

0

1

0

0

0

0

1

1

43

0

0

1

1

1

0

0

1

39

1

1

0

0

0

0

0

0

C0

+1

BX->AR

0663

1

0

1

0

0

0

0

0

A0

0

0

0

0

0

1

1

0

06

0

0

0

1

0

0

1

0

12

0001

RS->RAM

0680

0

0

0

0

0

1

1

1

07

0

0

0

0

0

1

0

0

04

0

0

0

0

0

0

0

0

00

+1

ROM->BL

0681

0

1

0

0

0

1

1

0

46

0

0

0

0

0

1

0

0

04

0

0

0

0

0

0

0

0

00

+1

ROM->BH

0682

1

1

0

0

0

0

0

1

C1

0

0

0

0

0

0

0

1

01

1

1

0

1

0

0

1

0

D2

0001

BX->PC

6A0

0

0

0

0

0

1

0

1

05

0

0

1

1

1

1

0

0

3C

0

0

0

0

0

0

0

0

00

+1

ROM->BL

6A1

0

1

0

0

0

1

0

0

44

0

0

1

1

1

1

0

0

3C

0

0

0

0

0

0

0

0

00

+1

ROM->BH

6A2

0

0

1

1

1

1

0

1

40

0

0

1

1

1

0

0

0

38

0

0

0

0

0

0

1

1

03

06A4

Decision 0 flag

06A4

0

0

0

0

0

0

0

0

00

0

0

1

1

1

0

0

0

38

0

0

0

1

0

0

1

0

12

0001

Empty operation

06A5

1

1

0

0

0

0

0

0

C1

0

0

1

1

1

0

0

1

38

0

0

1

0

1

1

0

1

D2

0001

BX->PC

06C0

1

1

1

1

1

0

1

0

05

1

1

1

1

1

0

1

1

04

0

0

0

0

0

0

0

0

00

+1

ROM->BL

06C1

0

1

0

0

0

1

0

0

44

0

0

0

0

0

1

0

0

04

0

0

0

0

0

0

0

0

00

+1

ROM->BH

06C2

0

0

0

0

0

0

0

0

40

0

0

0

0

0

0

0

0

00

0

0

0

0

1

0

0

1

05

06C4

Judge CY flag

06C4

0

0

0

0

0

0

0

0

00

0

0

0

0

0

0

0

0

00

0

0

0

1

0

0

1

0

12

0001

Empty operation

06C5

1

1

0

0

0

0

0

0

C1

0

0

1

0

1

0

0

1

39

1

1

0

1

0

0

1

0

D2

0001

BX->PC

06E0

0

0

0

0

0

1

1

1

07

0

0

0

0

0

1

1

1

07

1

1

0

0

0

0

0

0

C0

+1

PC->AX

06E1

1

1

0

0

0

0

0

0

C0

0

0

1

0

1

0

0

1

29

1

1

0

1

0

0

1

0

D2

06E0

AX-1->PC

0700

0

0

0

0

0

1

1

1

07

0

0

0

0

0

1

1

0

06

1

0

0

0

1

0

0

0

88

+1

RD->AX

0701

0

0

0

0

0

1

0

1

05

0

0

0

0

0

1

1

0

06

0

0

0

0

0

0

0

0

00

+1

RS->BX

0702

0

0

0

0

1

1

1

1

0F

1

0

0

1

0

0

0

0

91

1

0

0

1

0

0

1

0

92

0001

AX-BX->RD

0720

0

0

0

0

0

1

1

1

07

0

0

0

0

0

1

1

0

06

1

0

0

0

0

0

0

0

80

+1

RD->AX 

0721

0

0

0

0

0

1

0

1

05

0

0

0

0

0

1

1

0

06

0

0

0

0

0

0

0

0

00

+1

RS->BX

0722

0

0

0

0

1

1

1

1

0F

1

0

0

1

1

0

0

1

99

1

0

0

1

0

0

1

0

92

0001

AX+BX->RD

0740

0

0

0

0

0

1

1

1

07

0

0

0

0

0

1

1

0

06

1

0

0

0

0

0

0

0

80

+1

RD->AX

0741

0

0

0

0

0

1

0

1

05

0

0

0

0

0

1

1

0

06

0

0

0

0

0

0

0

0

00

+1

RS->BX

0742

0

0

0

0

1

1

1

1

0F

0

0

0

1

0

0

0

1

11

1

0

0

1

0

0

1

0

92

0001

AX&BX->RD

0760

0

0

0

0

0

1

1

1

07

0

0

0

0

0

1

1

0

06

1

0

0

0

0

0

0

0

80

+1

RD->AX

0761

0

0

0

0

1

1

1

1

0F

0

0

1

0

1

0

0

1

29

1

0

0

1

0

0

1

0

92

0001

AX-1->RD

0780

0

0

0

0

0

1

1

1

07

0

0

0

0

0

1

1

0

06

1

0

1

0

0

0

0

0

A0

+1

     RD->AX

0781

0

0

0

0

1

1

1

1

0F

0

0

1

0

0

0

0

1

21

1

0

1

1

0

0

1

0

B2

0001

AX=0->RD

07A0

0

0

0

0

0

1

1

1

07

0

0

0

0

0

1

1

0

06

1

0

0

0

0

0

0

0

80

+1

RD->AX

07A1

0

0

0

0

1

1

1

1

0F

1

0

1

0

1

0

0

1

A9

1

0

0

1

0

0

1

0

92

0001

RL AX->RD

07C0

0

0

0

0

0

1

1

1

07

0

0

0

0

0

1

1

0

06

1

0

0

0

0

0

0

0

80

+1

RD->AX

07C1

0

0

0

0

1

1

1

1

0F

1

0

1

0

0

0

0

1

A1

1

0

0

1

0

0

1

0

92

0001

RR AX->RD

07E0

0

0

0

0

1

1

1

1

0F

0

0

0

0

0

1

1

0

06

0

0

0

1

0

0

1

0

12

0001

Rd=Rs

8, Verification procedure

Procedure I:

; Curriculum design check procedure 1, including 12 instructions except jump instructions: add,and,dec,ldi,clr,rl,rr,ldr,sta,mov,out,hlt

#LOAD "test1.IS"  ; Pre call in the instruction system / microprogram and use its own microprogram file name

    org   0

       

start:

LDI  r0,12h

sta 100h,r0

lda r1,100h

dec r1

rl r0

add r0,r1

rrc r0

add r0,r1

ldi r2,76h

and r2,r0

mov r3,r2

add r3,r1

clr r0

out ioh,r3

halt

;qq:jmp qq

  End

Procedure 2:

; Curriculum design check procedure 2, including 3 jump instructions: jz,jc,jmp

#LOAD "test.IS"  ; Pre call in the instruction system / microprogram and use its own microprogram file name

    org   0

start:

ldi r0,12h

sub r0,r0

jz p1

ldi r0,0eeh

p1:ldi r1,11h

ldi r2,0ffh

add r1,r2

jc p2

ldi r1,0eeh

jmp p3

p2:ldi r1,11h

p3:ldi r2,22h

ldi r3,011h

add r3,r2

jc p4

jmp p5

p4:ldi r2,0eeh

p5:halt



  end

Inspection results:

Check1:

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  • Existing problems and experience
  1. The HALT termination instruction is to take out the PC and put it in AX. After ALU makes A-1, it is re assigned to the PC, and then the PC jumps back and PC + + after 0001. It is equivalent to continuously cycling the operation of PC-1+1=PC. the deadlock is in the cycle and plays the role of termination.
  2. CY carry / Z zero setting jump is to jump to the next address of the microinstruction address of the address transfer when the flag bit is 1, otherwise directly jump to the microinstruction address entry of the address transfer
  3. When it comes to the immediate number, it is necessary to put the address storing the immediate number behind the ROM and store AX/BX, which is transferred to AR / output to the specified register through ALU
  4. The function of division register and register. Register is a high-speed storage component with limited storage capacity, which can be used to temporarily store instructions, data and addresses; The register temporarily stores a certain amount of data. For example, a certain logic signal is often used many times during programming, and the intermediate results need to be memorized temporarily.

Tags: Windows

Posted by maxx99 on Mon, 18 Apr 2022 23:10:41 +0930